Half bridge circuits and H-bridge circuits (hereinafter generally referred to as “bridge output circuits”) using power transistors are being widely used for various kinds of electronic circuits. A bridge output circuit includes a high side transistor and a low side transistor connected in series between a power source terminal and a ground terminal When the high side transistor and the low side transistor alternate between a turning-on state and a turning-off state with a dead time being provided therebetween, an output voltage (also called a switching voltage) repeating a power source voltage or a ground voltage is outputted to a load from an output terminal which is a node between the high side transistor and the low side transistor.
A speed of change in a slope of the switching voltage (slew rate) becomes important in the bridge output circuit. In general, if the slew rate is too small, a waveform of the switching voltage becomes to be blunted. Thus, the slew rate is required to have a certain size.
On the other hand, if the slew rate is too large, high frequency components included in the switching voltage are increased. Since the high frequency components act as undesirable noise depending on usage environment of the bridge output circuit, there is a need to restrict the slew rate of the switching voltage within a certain range.
FIG. 1 is a circuit diagram of a conventional bridge output circuit 100r. The bridge output circuit 100r includes a high side transistor M1, a low side transistor M2, an output terminal Po, an upper power line LVDD, a lower power line LVSS, a controller 10r, a high side driver 20r and a low side driver 30r. 
The high side transistor M1 and the low side transistor M2 are connected in series between the upper power line LVDD and the lower power line LVSS.
The low side driver 30r applies a gate voltage VG2 assuming a high level voltage V2H or a low level voltage V2L to a gate of the low side transistor M2. The low side driver 30r includes a first current source CS2D and a second current source CS1D. The first current source CS2D and the second current source CS1D are configured to switch between a turning-on state and a turning-off state, independently.
Under a state where the low side transistor M2 is turned off, when the current source CS2D is turned on and the current source CS1D is turned off, a predetermined constant current I2D is supplied to a gate capacitance of the low side transistor M2 and the gate voltage VG2 increases to the high level voltage V2H, thereby turning on the low side transistor M2.
Under a state where the low side transistor M2 is turned on, when the current source CS2D is turned off and the current source CS1D is turned on, a predetermined constant current I1D is drawn from the gate capacitance of the low side transistor M2 and the gate voltage VG2 decreases to the low level voltage V2L, thereby turning off the low side transistor M2.
The high side driver 20r has a same configuration as the low side driver 30r. The high side driver 20r applies a gate voltage VG1 assuming a high level voltage V1H or a low level voltage V1L to a gate of the high side transistor M1, thereby switching the high side transistor M1.
The controller 10r controls an on/off state of current sources of the high side driver 20r and the low side driver 30r based on a control signal SIN.
FIG. 2 is a view showing a voltage-current characteristic of the low side transistor M2. FIG. 3 is a waveform diagram showing an operation of the bridge output circuit 100r of FIG. 1. FIG. 3 shows a waveform when an output voltage Vo transitions from a low level voltage VSS (for example, 0V) to a high level voltage VDD (for example, 12V). It is here assumed that a constant current source (not shown) as a virtual load is connected to the output terminal Po and load current Io flows in a direction (sink direction) in which the bridge output circuit 100r absorbs the load current Io. In an initial state, the high side transistor M1 is turned on and the low side transistor M2 is turned off, and the gate voltage VG2 is maintained around the high level voltage V2H (for example, 5V).
At time t0 (at which Period T1 starts), the control signal SIN transitions from a low level to a high level. Upon the transition of the control signal SIN, the controller 10r turns off the current source CS2D and turns on the current source CS1D, a gate capacitance (Cgs+Cgd) of the low side transistor M2 is discharged by the current LID, and the gate voltage VG2 gets lowered (Period T1 in FIG. 3).
When the gate voltage VG2 is lowered to a certain extent, on-resistance Ron of the low side transistor M2 begins to increase and the output voltage Vo (i.e., a drain-source voltage Vds) begins to increase as well (Period T2). This operation corresponds to a linear region I in FIG. 2.
A slew rate of the output voltage Vo is controlled in a subsequent slew rate control period T3. In the slew rate control period T3, the low side transistor M2 is operated in a saturation region II in FIG. 2. When source-drain current Ids is maintained at a constant value Io′, the gate voltage VG is changed in a narrow range (referred to as a “slew rate control region (Vslew)” in the specification) around Vgs=1V in the saturation region II in response to a change in the drain-source voltage Vds.
When the load current Io is constant, in order to change the output voltage Vo with a constant slope, there is a need to change on-resistance of the low side transistor M2 with a constant slope. In the slew rate control period T3, the output voltage Vo (Vds) increases with the constant slope, whereas the gate voltage VG2 keeps substantially constant. Accordingly, it is to be noted that a gate-drain capacitance Cgd of the high side transistor M1 is dominant and the current I1D acts on the gate-drain capacitance Cgd.
When the current source CS1D of the low side driver 30 generates the constant current I1D, the gate voltage VG2 is changed such that on-resistance of the high side transistor M1 decreases with a constant slope and, consequently, the output voltage Vo can be changed with a constant slope.
The inventor has reviewed the bridge output circuit 100r and was aware of the following problem.
A range of the load current Io may be dynamically varied depending on a load connected to the bridge output circuit 100r. Accordingly, in the voltage-current characteristic in FIG. 2, the slew rate control region Vslew is heightened if the load current Io is large (for example, 500 mA) and is lowered if the load current Io is small (for example, 100 mA).
FIGS. 4A and 4B are waveform diagrams showing the output voltage Vo and the gate voltage VG2 when the load current Io is 500 mA and 100 mA, respectively. The length of the period T1 is equal to time taken until the gate voltage VG2 decreases from an initial value, i.e., the high level voltage V2H, to around an upper limit of the slew rate control region Vslew. Accordingly, when the load current Io is small and the slew rate control region Vslew is lowered, there rises a problem of prolongation of the period T1 i.e., there may be an increase in a sponse delay of the output voltage Vo to the control signal SIN. Such increase in the response delay results in an increased power loss of the bridge output circuit 100r and hence poor efficiency. This problem should not be taken by those skilled in the art as general technical recognition but is one revealed by independent investigation by the inventor. The same problem may be raised in the side of the high side transistor M1.